The present disclosure relates to a semiconductor memory device, and particularly to the detection of a memory cell failure.
Transistor elements are being miniaturized for high integration. In parallel with miniaturization, voltage scaling is needed from the viewpoint of transistor element reliability and power consumption. However, when the transistor elements are miniaturized, an error in a manufacturing process (mask misalignment and impurity implantation quantity error) exerts a significant influence so that the characteristics of transistor elements greatly vary. Therefore, a write margin decreases, for example, in an SRAM (static random-access memory), thereby causing a problem in which an operating margin is decreased.
As a method of addressing the above problem, a write operation failure may be prevented by applying a negative voltage to a bit line during a write operation in order to increase the current drive capability of an access MOS transistor in a memory cell (refer to Japanese Unexamined Patent Application Publication No. 2009-295246 and J. Chang, et al, “A 20 nm 112 Mb SRAM Design in High K/Metal Gate Technology with Assist Circuitry for Low Leakage and Low Vmin Applications”, ISSCC '13).
According to Japanese Unexamined Patent Application Publication No. 2009-295246, a boost circuit is formed of a boost capacitor and an inverter driving the boost capacitor is provided and coupled to bit line pairs through switches. A method described in this patent literature is to transfer a negative voltage by selecting a switch on the bit line side, which is driven by a ground potential.
According to “A 20 nm 112 Mb SRAM Design in High K/Metal Gate Technology with Assist Circuitry for Low Leakage and Low Vmin Applications”, an inverter is provided as a write drive circuit for each bit line pair. Sources of two write inverters are short-circuited and coupled to a low-voltage side power supply VSS through a power switch. A boost capacitor is coupled to the short-circuited sources of the write inverters. When the power switch is turned off, only the output node of an inverter on the ground voltage output side is placed in a floating state. A method described in this patent literature is to transfer a boosted negative voltage to a bit line through the NMOS and Y switch of a write inverter that outputs a ground voltage.